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Espressif Systems /ESP32-C6 /PCR /PVT_MONITOR_FUNC_CLK_CONF

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Interpret as PVT_MONITOR_FUNC_CLK_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PVT_MONITOR_FUNC_CLK_DIV_NUM 0 (PVT_MONITOR_FUNC_CLK_SEL)PVT_MONITOR_FUNC_CLK_SEL 0 (PVT_MONITOR_FUNC_CLK_EN)PVT_MONITOR_FUNC_CLK_EN

Description

PVT_MONITOR function clock configuration register

Fields

PVT_MONITOR_FUNC_CLK_DIV_NUM

The integral part of the frequency divider factor of the pvt_monitor function clock.
PVT_MONITOR_FUNC_CLK_SEL

set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL divided by 3.
PVT_MONITOR_FUNC_CLK_EN

Set 1 to enable source clock of pvt sitex

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data